This paper presents a data-compressive neural recording IC for single-cell resolution high-bandwidth brain-computer interfaces. The IC features wired-OR lossy compression during digitization, thus preventing data deluge and massive data movement. By discarding unwanted baseline samples of the neural signals, the output data rate is reduced by 146× on average while allowing the reconstruction of spike samples. The recording array consists of pulse position modulation-based active digital pixels with a global single-slope analog-to-digital conversion scheme, which enables a low-power and compact pixel design with significantly simple routing and low array readout energy. Fabricated in a 28-nm CMOS process, the neural recording IC features 1024 channels (i.e., 32 × 32 array) with a pixel pitch of 36 m that can be directly matched to a high-density microelectrode array. The pixel achieves 7.4 V input-referred noise with a -3 dB bandwidth of 300-Hz to 5-kHz while consuming only 268 nW from a single 1-V supply. The IC achieves the smallest area per channel (36 × 36 m) and the highest energy efficiency among the state-of-the-art neural recording ICs published to date.

The current demand for high-channel-count neural-recording interfaces calls for more area- and power-efficient readout architectures that do not compromise other electrical performances. In this paper, we present a miniature 128-channel neural recording integrated circuit (NRIC) for the simultaneous acquisition of local field potentials (LFPs) and action potentials (APs), which can achieve a very good compromise between area, power, noise, input range and electrode DC offset cancellation. An AC-coupled 1-order digitally-intensive architecture is proposed to achieve this compromise and to leverage the advantages of a highly-scaled technology node. A prototype NRIC, including 128 channels, a newly-proposed area-efficient bulk-regulated voltage reference, biasing circuits and a digital control, has been fabricated in 22-nm FDSOI CMOS and fully characterized. Our proposed architecture achieves a total area per channel of 0.005 mm, a total power per channel of 12.57 , and an input-referred noise of 7.7 ± 0.4 in the AP band and 11.9 ± 1.1 in the LFP band. A very good channel-to-channel uniformity is demonstrated by our measurements. The chip has been validated , demonstrating its capability to successfully record full-band neural signals.

This paper presents an implantable impulse-radio ultra-wideband (IR-UWB) wireless telemetry system for intracortical neural sensing interfaces. A 3-dimensional (3-D) hybrid impulse modulation that comprises phase shift keying (PSK), pulse position modulation (PPM) and pulse amplitude modulation (PAM) is proposed to increase modulation order without significantly increasing the demodulation requirement, thus leading to a high data rate of 1.66 Gbps and an increased air-transmission range. Operating in 6 - 9 GHz UWB band, the presented transmitter (TX) supports the proposed hybrid modulation with a high energy efficiency of 5.8 pJ/bit and modulation quality (EVM< -21 dB). A low-noise injection-locked ring oscillator supports 8-PSK with a phase error of 2.6°. A calibration free delay generator realizes a 4-PPM with only 115 μW and avoids potential cross-modulation between PPM and PSK. A switch-cap power amplifier with an asynchronous pulse-shaping performs 4-PAM with high energy efficiency and linearity. The TX is implemented in 28 nm CMOS technology, occupying 0.155mm core area. The wireless module including a printed monopole antenna has a module area of only 1.05 cm. The transmitter consumes in total 9.7 mW when transmitting -41.3 dBm/MHz output power. The wireless telemetry module has been validated with a 15-mm multi-layer porcine tissue, and achieves a communication (air) distance up to 15 cm, leading to at least 16× improvement in distance-moralized energy efficiency of 45 pJ/bit/meter compared to state-of-the-art.

This paper presents a fully integrated RF energy harvester (EH) with 30% end-to-end power harvesting efficiency (PHE) and supports high output voltage operation, up to 9.3V, with a 1.07 GHz input and under the electrode model for neural applications. The EH is composed of a novel 10-stage self-biased gate (SBG) rectifier with an on-chip matching network. The SBG topology elevates the gate-bias of transistors in a non-linear manner to enable higher conductivity. The design also achieves >20% PHE range of 12-dB. The design was fabricated in 65 nm CMOS technology and occupies an area of 0.0732-mm with on-chip matching network. In addition to standalone EH characterization measurement results, animal tissue stimulation test was performed to evaluate its performance in a realistic neural implant application.

Single modality wireless power transfer has limited depth for mm-sized implants across air / tissue or skull / tissue interfaces because they either suffer from high loss in tissue (RF, Optical) or high reflection at the medium interface (Ultrasound (US)). This paper proposes an RF-US relay chip at the media interface avoiding the reflection at the boundary, and enabling efficient wireless powering to mm-sized deep implants across multiple media. The relay chip rectifies the incoming RF power through an 85.5% efficient RF inductive link (across air) using a multi-output regulating rectifier (MORR) with 81% power conversion efficiency (PCE) at 186 mW load, and transmits ultrasound using adiabatic power amplifiers (PAs) to the implant in order to minimize cascaded power loss. To adapt the US focus to implant movement or placement, beamforming was implemented using 6 channels of US PAs with 2-bit phase control (0, 90, 180, and 270°) and 3 different amplitudes (6-29, 4.5, and 1.8 V) from the MORR. The adiabatic PA contributes a 30-40% increase in efficiency over class-D and beamforming increases the efficiency by 251% at 2.5 cm over fixed focusing. The proof-of-concept powering system for a retinal implant, from an external PA on a pair of glasses to a hydrophone with 1.2 cm (air) + 2.9 cm (agar eyeball phantom in mineral oil) separation distance, had a power delivered to the load (PDL) of 946 W. The 2.3 × 2 mm relay chip was fabricated in a 180 nm high-voltage (HV) BCD process.

This paper presents a bio-inspired event-driven neuromorphic sensing system (NSS) capable of performing on-chip feature extraction and "send-on-delta" pulse-based transmission, targeting peripheral-nerve neural recording applications. The proposed NSS employs event-based sampling which, by leveraging the sparse nature of electroneurogram (ENG) signals, achieves a data compression ratio of >125×, while maintaining a low normalized RMS error of 4% after reconstruction. The proposed NSS consists of three sub-circuits. A clockless level-crossing (LC) ADC with background offset calibration has been employed to reduce the data rate, while maintaining a high signal to quantization noise ratio. A fully synthesized spiking neural network (SNN) extracts temporal features of compound action potential signals consumes only 13 μW. An event-driven pulse-based body channel communication (Pulse-BCC) with serialized address-event representation encoding (AER) schemes minimizes transmission energy and form factor. The prototype is fabricated in 40-nm CMOS occupying a 0.32-mm active area and consumes in total 28.2 μW and 50 μW power in feature extraction and full diagnosis mode, respectively. The presented NSS also extracts temporal features of compound action potential signals with 10-μs precision.

Wake-up receivers (WuRX) present an opportunity to reduce average power consumption of IoT transceivers, however achieving sensitivity and interferer tolerance while providing wideband matching and sharing an antenna interface present a significant challenge for existing architectures. This paper presents a primary/WuRX which utilizes a quadrature hybrid coupler based N-Path mixer first architecture to simultaneously achieve low noise, wideband matching and a shared antenna interface. The passive-mixer first approach and a two-code modulated multi-tone signaling scheme provide interferer tolerance in the WuRX. The paper analyzes gain/power trade-offs in the proposed architecture in the context of noise impact with multi-tone WuRX signaling. The proposed architecture is implemented in 65 nm CMOS and occupies 2.25 . The primary RX achieves 3.8 dB NF and 0.75 dBm out-of-band P1dB with 440W power consumption. The WuRX achieves -86 dBm sensitivity for 10kb/s data rate and up to -40 dB signal-to-interferer ratio (SIR) with 171W power consumption.

Miniaturized and wireless near-infrared (NIR) based neural recorders with optical powering and data telemetry have been introduced as a promising approach for safe long-term monitoring with the smallest physical dimension among state-of-the-art standalone recorders. However, a main challenge for the NIR based neural recording ICs is to maintain robust operation in the presence of light-induced parasitic short circuit current from junction diodes. This is especially true when the signal currents are kept small to reduce power consumption. In this work, we present a light-tolerant and low-power neural recording IC for motor prediction that can fully function in up to 300 W/mm of light exposure. It achieves best-in-class power consumption of 0.57 W at 38° C with a 4.1 NEF pseudo-resistorless amplifier, an on-chip neural feature extractor, and individual mote level gain control. Applying the 20-channel pre-recorded neural signals of a monkey, the IC predicts finger position and velocity with correlation coefficient up to 0.870 and 0.569, respectively, with individual mote level gain control enabled. In addition, wireless measurement is demonstrated through optical power and data telemetry using a custom PV/LED GaAs chip wire bonded to the proposed IC.

This paper presents a hardware platform including stimulating implants wirelessly powered and controlled by a shared transmitter for coordinated leadless multisite stimulation. The adopted novel single-transmitter, multiple-implant structure can flexibly deploy stimuli, improve system efficiency, easily scale stimulating channel quantity and relieve efforts in device synchronization. In the proposed system, a wireless link leveraging magnetoelectric effects is co-designed with a robust and efficient system-on-chip to enable reliable operation and individual programming of every implant. Each implant integrates a 0.8-mm chip, a 6-mm magnetoelectric film, and an energy storage capacitor within a 6.2-mm size. Magnetoelectric power transfer is capable of safely transmitting milliwatt power to devices placed several centimeters away from the transmitter coil, maintaining good efficiency with size constraints and tolerating 60-degree, 1.5-cm misalignment in angular and lateral movement. The SoC robustly operates with 2-V source amplitude variations that spans a 40-mm transmitter-implant distance change, realizes individual addressability through physical unclonable function IDs, and achieves 90% efficiency for 1.5-to-3.5-V stimulation with fully programmable stimulation parameters.

Electrophysiological research on neural networks and their activity focuses on the recording and analysis of large data sets that include information of thousands of neurons. CMOS microelectrode arrays (MEAs) feature thousands of electrodes at a spatial resolution on the scale of single cells and are, therefore, ideal tools to support neural-network research. Moreover, they offer high spatio-temporal resolution and signal to-noise ratio (SNR) to capture all features and subcellular resolution details of neuronal signaling. Here, we present a dual-mode (DM) MEA, which enables simultaneous: 1) full-frame readout from all electrodes and 2) high-SNR readout from an arbitrarily selectable subset of electrodes. The DM-MEA includes 19584 electrodes, 19584 full-frame recording channels with noise levels of 10.4 V in the action potential (AP) frequency band (300 Hz-5 kHz), 246 low-noise recording channels with noise levels of 3.0 V in the AP band and eight stimulation units. The capacity to simultaneously perform full-frame and high-SNR recordings endows the presented DM-MEA with great flexibility for various applications in neuroscience and pharmacology.

We present a 180-nm CMOS bidirectional neural interface system-on-chip that enables simultaneous recording and stimulation with on-chip stimulus artifact cancelers. The front-end cancellation scheme incorporates a least-mean-square engine that adapts the coefficients of a 2-tap infinite-impulse-response filter to replicate the stimulation artifact waveform and subtract it at the front-end. Measurements demonstrate the efficacy of the canceler in mitigating artifacts up to 700 mV and reducing the front-end amplifier saturation recovery time in response to a 2.5 V artifact. Each recording channel houses a pair of adaptive infinite-impulse-response filters, which enable cancellation of the artifacts generated by the simultaneous operation of the 2 on-chip stimulators. The analog front-end consumes 2.5 W of power per channel, has a maximum gain of 50 dB and a bandwidth of 9.0 kHz with 6.2 V integrated input-referred noise.

A single-inductor self-starting boost converter is presented suitable for thermoelectric energy harvesting from human body heat. In order to extract maximum energy from a thermoelectric generator (TEG) at small temperature gradients, a loss-aware maximum power point tracking (MPPT) scheme was developed that enables the harvester to achieve high end-to-end efficiency at low input voltages. The boost converter is implemented in a 0.18 μm CMOS technology and is more than 75% efficient for a matched input voltage range of 15 mV-100 mV, with a peak efficiency of 82%. Enhanced power extraction enables the converter to sustain operation at an input voltage as low as 3.5 mV. In addition, the boost converter self-starts with a minimum TEG voltage of 50 mV leveraging a dual-path architecture without using additional off-chip components.

This paper presents a millimeter-scale CMOS 64×64 single charged particle radiation detector system for external beam cancer radiotherapy. A 1×1 m diode measures energy deposition by a single charged particle in the depletion region, and the array design provides a large detection area of 512×512 m. Instead of sensing the voltage drop caused by radiation, the proposed system measures the pulse width, i.e., the time it takes for the voltage to return to its baseline. This obviates the need for using power-hungry and large analog-to-digital converters. A prototype ASIC is fabricated in TSMC 65 nm LP CMOS process and consumes the average static power of 0.535 mW under 1.2 V analog and digital power supply. The functionality of the whole system is successfully verified in a clinical 67.5 MeV proton beam setting. To our' knowledge, this is the first work to demonstrate single charged particle detection for implantable dosimetry.

This paper presents a batteryless heartbeat detection system-on-chip (SoC) powered by human body heat. An adaptive threshold generation architecture using pulse-width locked loop (PWLL) is developed to detect heartbeats from electrocardiogram (ECG) in the presence of motion artifacts. The sensing system is autonomously powered by harvesting thermal energy from human body heat using a thermoelectric generator (TEG) coupled to a low-voltage, self-starting boost converter and integrated power management system. The SoC was implemented in a 0.18 μm CMOS process and is fully functional with a minimum input power of 20 μW, provided by a portable TEG at 20 mV with a ~0.5 °C temperature gradient. The complete system demonstrates motion-adaptive, power-autonomous heartbeat detection for sustainable healthcare using wearable devices.

In this paper, we present the design and the analysis of an electrochemical circuit for measuring the concentrations of therapeutic drugs using structure-switching aptamers. Aptamers are single-stranded nucleic acids, whose sequence is selected to exhibit high affinity and specificity toward a molecular target, and change its conformation upon binding. This property, when coupled with a redox reporter and electrochemical detection, enables reagent-free biosensing with a sub-minute temporal resolution for therapeutic drug monitoring. Specifically, we design a chronoamperometry-based electrochemical circuit that measures the direct changes in the electron transfer (ET) kinetics of a methylene blue reporter conjugated at the distal-end of the aptamer. To overcome the high-frequency noise amplification issue when interfacing with a large-size (> 0.25 mm) implantable electrode, we present a sample-and-hold (S/H) circuit technique in which the desired electrode potentials are held onto noiseless capacitors during the recording of the redox currents. This allows disconnecting the feedback amplifiers to avoid its noise injection while reducing the total power consumption. A prototype circuit implemented in 65-nm CMOS demonstrates a cell-capacitance-insensitive input-referred noise (IRN) current of 15.2 pA at a 2.5-kHz filtering bandwidth. We tested our system in human whole blood samples and measured the changes in the ET kinetics from the redox-labeled aptamers at different kanamycin concentrations. By employing principal component analysis (PCA) to compensate for the sampling errors, we report a molecular noise floor (at SNR = 1) of 3.1 µM with sub 1-sec acquisition time at 0.22-mW power consumption.

CMOS microelectrode arrays (MEAs) can record electrophysiological activities of a large number of neurons in parallel but only extracellularly with low signal-to-noise ratio. Patch clamp electrodes can perform intracellular recording with high signal-to-noise ratio but only from a few neurons in parallel. Recently we have developed and reported a neuroelectronic interface that combines the parallelism of the CMOS MEA and the intracellular sensitivity of the patch clamp. Here, we report the design and characterization of the CMOS integrated circuit (IC), a critical component of the neuroelectronic interface. Fabricated in 0.18-m technology, the IC features an array of 4,096 platinum black (PtB) nanoelectrodes spaced at a 20 m pitch on its surface and contains 4,096 active pixel circuits. Each active pixel circuit, consisting of a new switched-capacitor current injector--capable of injecting from ±15 pA to ±0.7 A with a 5 pA resolution--and an operational amplifier, is highly configurable. When configured into current-clamp mode, the pixel intracellularly records membrane potentials including subthreshold activities with ∼23 V input referred noise while injecting a current for simultaneous stimulation. When configured into voltage-clamp mode, the pixel becomes a switched-capacitor transimpedance amplifier with ∼1 pA input referred noise, and intracellularly records ion channel currents while applying a voltage for simultaneous stimulation. Such voltage/current-clamp intracellular recording/stimulation is a feat only previously possible with the patch clamp method. At the same time, as an array, the IC overcomes the lack of parallelism of the patch clamp method, measuring thousands of mammalian neurons in parallel, with full-frame intracellular recording/stimulation at 9.4 kHz.

In this article, we present a highly integrated guidewire ultrasound (US) imaging system-on-a-chip (GUISoC) for vascular imaging. The SoC consists of a 16-channel US transmitter (Tx) and receiver (Rx) electronics, on-chip power management IC (PMIC), and quadrature sampler. Using a synthetic aperture imaging algorithm, a Tx/Rx pair, connected to capacitive micromachined ultrasound transducers (CMUTs), can be activated at any time. The Tx generates acoustic waves by driving the CMUT, while the Rx picks up the echo signal and amplify it to be delivered through an interconnect that is driven by a buffer. On-chip logic controls the pulsers that generate the high-voltage (HV)-pulse for Tx. An on-chip PMIC provides 1.8-, 5-, 39-, and 44-V supplies and a clock signal from the two interconnects besides GND. A quadrature sampler down-converts the Rx echo signal to baseband, reducing its bandwidth requirement for the output interconnect. The system design, including transimpedance amplifier (TIA) optimization, based on the equivalent circuit of a specific CMUT is presented. The SoC was fabricated by a 0.18-m HV CMOS process, occupying 1.5-mm2 active area and consuming 25.2 and 44 mW from 1.8 to 44 V supplies, respectively. The US Tx and Rx show bandwidths of 32-42 and 32.7-37.5 MHz, respectively. The input-referred noise of the system was measured as 9.66 nA in band with 2-m-long 52 American Wire Gauge (AWG) wire interconnects. The functionality of the GUISoC was verified by imaging wire targets.

We present an implantable single photon shank-based imager, monolithically integrated onto a single CMOS IC. The imager comprises of 512 single photon avalanche diodes distributed along two shanks, with a 6-bit depth in-pixel memory and an on-chip digital-to-time converter. To scale down the system to a minimally invasive form factor, we substitute optical filtering and focusing elements with a time-gated, angle-sensitive detection system. The imager computationally reconstructs the position of fluorescent sources within a three-dimensional volume of 3.4 mm × 600 m × 400 m.

This paper demonstrates an on-chip electrical cold-start technique to achieve low-voltage and fast start up of a boost converter for autonomous thermal energy harvesting from human body heat. An improved charge transfer through high gate-boosted switches by means of cross-coupled complementary charge pumps enables voltage multiplication of the low input voltage during cold start. The start-up voltage multiplier operates with an on-chip clock generated by an ultra-low-voltage ring oscillator. The proposed cold-start scheme implemented in a general purpose 0.18μm CMOS process assists an inductive boost converter to start operation with a minimum input voltage of 57mV in 135 ms while consuming only 90 nJ of energy from the harvesting source, without using additional sources of energy or additional off-chip components.

An integrated power management (IPM) with the unique capabilities of seamless-voltage/current-mode (SVCM) operation and energy recycling is presented for robust inductive power delivery. Utilizing parasitic bulk diodes with lower voltage drop, this IPM seamlessly transitions between voltage mode (VM) and current mode (CM) in a safe and robust fashion, extending the input-voltage range (removing dead zone) and significantly improving power-conversion efficiency (PCE) in CM operation. The IPM first provides the required load power (P) by one-step rectification/regulation, and then stores the surplus energy into a storage capacitor to extend the receiver (Rx) operation time via energy recycling when the input power is insufficient. The theory behind the energy recycling is presented. A proof-of-concept chip was fabricated in a 0.35 µm CMOS process. In measurements, the chip safely achieved a regulated voltage of 3 V for a wide input-voltage range (without dead zone) by switching the Rx LC-tank at 142 kHz. With zero input power, the chip extended the Rx operation time by 250% thanks to the energy recycling.

Closed-loop neural interfaces with on-chip machine learning can detect and suppress disease symptoms in neurological disorders or restore lost functions in paralyzed patients. While high-density neural recording can provide rich neural activity information for accurate disease-state detection, existing systems have low channel counts and poor scalability, which could limit their therapeutic efficacy. This work presents a highly scalable and versatile closed-loop neural interface SoC that can overcome these limitations. A 256-channel time-division multiplexed (TDM) front-end with a two-step fast-settling mixed-signal DC servo loop (DSL) is proposed to record high-spatial-resolution neural activity and perform channel-selective brain-state inference. A tree-structured neural network (NeuralTree) classification processor extracts a rich set of neural biomarkers in a patient- and disease-specific manner. Trained with an energy-aware learning algorithm, the NeuralTree classifier detects the symptoms of underlying disorders (e.g., epilepsy and movement disorders) at an optimal energy-accuracy trade-off. A 16-channel high-voltage (HV) compliant neurostimulator closes the therapeutic loop by delivering charge-balanced biphasic current pulses to the brain. The proposed SoC was fabricated in 65nm CMOS and achieved a 0.227μJ/class energy efficiency in a compact area of 0.014mm/channel. The SoC was extensively verified on human electroencephalography (EEG) and intracranial EEG (iEEG) epilepsy datasets, obtaining 95.6%/94% sensitivity and 96.8%/96.9% specificity, respectively. neural recordings using soft μECoG arrays and multi-domain biomarker extraction were further performed on a rat model of epilepsy. In addition, for the first time in literature, on-chip classification of rest-state tremor in Parkinson's disease (PD) from human local field potentials (LFPs) was demonstrated.