Ion gel-based dielectrics have long been considered for enabling low-voltage operation in printed thin-film transistors (TFTs), but their compatibility with in-place printing (a streamlined, direct-write printing approach where devices never leave the printer mid- or post-process) remains unexplored. Here, we demonstrate a simple and rapid 4-step in-place printing procedure for producing low-voltage electrolyte-gated carbon nanotube (CNT) thin-film transistors at low temperature (80 °C). This process consists of the use of polymer-wrapped CNT inks for printed channels, silver nanowire inks for printed electrodes, and imidazolium-based ion gel inks for printed gate dielectrics. We find that the efficacy of rinsing CNT films and printing an ion gel in-place is optimized using an elevated platen temperature (as opposed to external rinsing or post-process annealing), where resultant devices exhibited on/off-current ratios exceeding 10, mobilities exceeding 10 cmVs, and gate hysteresis of only 0.1 V. Additionally, devices were tested under mechanical strain and long-term bias, showing exceptional flexibility and electrochemical stability over the course of 14-hour bias tests. The findings presented here widen the potential scope of print-in-place (PIP) devices and reveal new avenues of investigation for the improvement of bias stress stability in electrolyte-gated transistors.

Wearable and implantable pressure sensors are in great demand for personalized health monitoring. Pressure sensors with low operation voltage and low power-consumption are desired for energy-saving devices. Organic iontronic devices, such as organic electrochemical transistors (OECTs), have demonstrated great potential for low power-consumption bioelectronic sensing applications. The ability to conduct both electrons and ions, in addition to their low-operation voltage has enabled the widespread use of OECTs in different biosensing fields. However, despite these merits, OECTs have not been demonstrated for pressure sensing applications. This is because most OECTs are gated with aqueous electrolyte, which fails to respond to external pressure. Here, a low power-consumption iontronic pressure sensor is presented based on an OECT, in which an ionic hydrogel is used as a solid gating medium. The resultant iontronic device operated at voltages less than 1 V, with a power-consumption between ~ 10-10 W, while maintaining a tunable sensitivity between 1 ~ 10 kPa. This work places OECTs on the frontline for developing low power-consumption iontronic pressure sensors and for biosensing applications.

In this work, we present a CMOS-integrated low-noise junction field-effect transistor (JFET) developed in a standard 0.18 pm CMOS process. These JFETs reduce input-referred flicker noise power by more than a factor of 10 when compared to equally sized n-channel MOS devices by eliminating oxide interfaces in contact with the channel. We show that this improvement in device performance translates into a factor-of-10 reduction in the input-referred noise of integrated CMOS operational amplifiers when JFET devices are used at the input, significant for many applications in bioelectronics.

Wrap-around gate GaN nanowire MOSFETs using AlO as gate oxide have been experimentally demonstrated. The fabricated devices exhibit a minimum subthreshold slope of 60 mV/dec, an average subthreshold slope of 68 mV/dec over three decades of drain current, drain-induced barrier lowering of 27 mV/V, an on-current of 42 μA/μm (normalized by nanowire circumference), on/off ratio over 10, an intrinsic transconductance of 27.8 μS/μm, for a switching efficiency figure of merit, Q=g/SS of 0.41 μS/μm-dec/mV. These performance metrics make GaN nanowire MOSFETs a promising candidate for emerging low-power applications such as sensors and RF for the internet of things.

The stochastic nature of the conductive filaments in oxide-based resistive memory (RRAM) represents a sizeable impediment to commercialization. As such, program-verify methodologies are highly alluring. However, it was recently shown that program-verify methods are unworkable due to strong resistance state relaxation after SET/RESET programming. In this paper, we demonstrate that resistance state relaxation is not the main culprit. Instead, it is fluctuation-induced false-reading (triggering) that defeats the program-verify method, producing a large distribution tail immediately after programming. The fluctuation impact on the verify mechanism has serious implications on the overall write/erase speed of RRAM.

In this work, we use gated Hall method for direct measurement of free carrier density and electron mobility in inversion InGaAs MOSFET channels. At room temperature, the highest Hall mobility of 1800 cm/Vs is observed at electron density in the channel ≈1×10 cm. A comparison with mobility values estimated from transistor characteristics reveals a significant underestimation of mobility which arises from overestimation of channel density obtained from C-V measurements. Temperature dependence of the electron mobility provides the evidence that remote Coulomb scattering dominates at electron density < 3×10 cm. Contrary to the capacitance-based methods commonly used for extraction of interface trap density, gated Hall method can separate the contributions of fast-trapped charges and free carriers in the channel to the total charge of a MOS capacitor. This allows for reliable estimation of trap density at the III-V/high-k interface including border traps. The results illustrate that even high-quality interfaces providing high-mobility transport suffer from fast border traps above the conduction band. In contrast with Si where the effect of border traps is negligible, in low density-of-state InGaAs channel material as much as half of the channel electrons can be trapped and excluded from transport, increasing switching energy and dissipated power.