Ultrasound (US) as a wireless power transfer methodology has drawn considerable attention from the implantable medical devices (IMD) research community. Beamforming (BF) using an external transducer array patch (ETAP) has been proposed as a robust localization scheme to find a mm-sized IMD inside the human body. However, for applications focusing on deep and shallow IMDs, optimum resource utilization at the ETAP is a major power efficiency concern for energy-constrained wearable patches. Moreover, misalignment tolerance due to IMD movements (respiratory and patient ambulatory reasons) relative to the ETAP remains a challenge. This paper presents an energy-efficient method to localize a mm-sized IMD through the dynamic selection of a sub-array within the ETAP. It is fully adaptive to the heterogeneity of the media and requires no a priori knowledge of the IMD. To improve the tolerance to IMD movements, tracking is implemented by adding and subtracting elements on the sub-array such that the sub-array electrically follows the IMD movement. Furthermore, it is shown that a minimum sampling frequency of 10X the US frequency can improve the tolerance to random noise. K-wave simulations in MATLAB are performed in different heterogenous, scattering biological media to prove the efficacy of the proposed method over standard BF methods. Measurement results in heterogenous scattering media consisting of a 3D-printed human ribs phantom and a partially blocking multipath cancellous bone phantom show an energy efficiency improvement of 10.53X and 14.4X compared to the delay-and-sum beamforming method and the unfocused transmission employing all the elements of the ETAP, respectively.

High-throughput biosensor screening and optimization are critical for health and environmental monitoring applications to ensure rapid and accurate detection of biological and chemical targets. Traditional biosensor design and optimization methods involve labor-intensive processes, such as manual pipetting of large sample volumes, making them low throughput and inefficient for large-scale library screenings under various environmental and chemical conditions. We address these challenges by introducing a modular droplet microfluidic system embedded with custom CMOS integrated circuits (ICs) for impedance spectroscopy and bioluminescence detection. Fabricated in a 65 nm process, our CMOS ICs enable efficient droplet detection and analysis. We demonstrate successful sensing of luciferase enzyme-substrate reactions in nL-volume droplets. The impedance spectroscopy chip detects 4 nL droplets at 67 mm/s with a 45 pA resolution, while the luminescence detector senses optical signals from 38 nL droplets with a 6.7 nA/count resolution. We show real-time concurrent use of both detection methods within our hybrid platform for cross-validation. This system greatly advances conventional biosensor testing by increasing flexibility, scalability, and cost-efficiency.

This paper presents an application-specific integrated circuit (ASIC) fabricated using the CMOS 180 nm process to perform simultaneous neural recording and optogenetic stimulation. To perform effective optogenetic stimulation, the ASIC features an advanced switched-capacitor-based stimulation (SCS) driver, called voltage-boosting SCS (VB-SCS). The VB-SCS can drive LED with large current pulses up to 8 mA while reducing the required supply voltage by half, facilitating wireless power reception. To prevent saturation from stimulation-induced artifacts, the ASIC integrates a direct digitizing recording frontend with a high-resolution delta-sigma (ΔΣ) analog-to-digital converter (ADC) that directly digitizes neural signals with a large input dynamic range. This ΔΣ ADC involves a Gm-C integrator followed by a noise-shaping (NS) successive approximation register (SAR) quantizer. Measurement results indicate that this ΔΣ ADC-based direct digitizing frontend can tolerate large artifacts up to 300 mV while linearly digitizing neural signals with an effective number of bits (ENOB) of 11.4 bits, consuming 10.8 μW. The ASIC, together with its associated passive components, was assembled into a headstage for in vivo verification, successfully demonstrating the functionality of the ASIC.

Bio-inspired neuromorphic hardware with learning ability is highly promising to achieve human-like intelligence, particularly in terms of high energy efficiency and strong environmental adaptability. Though many customized prototypes have demonstrated learning ability, learning on neuromorphic hardware still lacks a bio-plausible and unified learning framework, and inherent spike-based sparsity and parallelism have not been fully exploited, which fundamentally limits their computational efficiency and scale. Therefore, we develop a unified, event-driven, and massively parallel multi-core neuromorphic online learning processor, namely EPOC. We present a neuromodulation-based neuromorphic online learning framework to unify various learning algorithms, and EPOC supports high-accuracy local/global supervised Spike Neural Network (SNN) learning with a low-memory-demand streaming single-sample learning strategy through different neuromodulator formulations. EPOC leverages a novel event-driven computation method that fully exploits spike-based sparsity throughout the forward-backward learning phases, and parallel multi-channel and multi-core computing architecture, bringing 9.9× time efficiency improvement compared with the baseline architecture. We synthesize EPOC in a 28-nm CMOS process and perform extensive benchmarking. EPOC achieves state-of-the-art learning accuracy of 99.2%, 98.2%, and 94.3% on the MNIST, NMNIST, and DVS-Gesture benchmarks, respectively. Local-learning EPOC achieves 2.9× time efficiency improvement compared with the global learning counterpart. EPOC operates at a typical clock frequency of 100 MHz, providing a peak 328 GOPS/51 GSOPS throughput and a 5.3 pJ/SOP energy efficiency.

Recent advancements in head-mounted wearable technology are revolutionizing the field of biopotential measurement, but the integration of these technologies into practical, user-friendly devices remains challenging due to issues with design intrusiveness, comfort, reliability, and data privacy. To address these challenges, this paper presents GAPSES, a novel smart glasses platform designed for unobtrusive, comfortable, and secure acquisition and processing of electroencephalography (EEG) and electrooculography (EOG) signals.We introduce a direct electrode-electronics interface within a sleek frame design, with custom fully dry soft electrodes to enhance comfort for long wear. The fully assembled glasses, including electronics, weigh 40 g and have a compact size of 160 mm × 145 mm. An integrated parallel ultra-low-power RISC-V processor (GAP9, Greenwaves Technologies) processes data at the edge, thereby eliminating the need for continuous data streaming through a wireless link, enhancing privacy, and increasing system reliability in adverse channel conditions. We demonstrate the broad applicability of the designed prototype through validation in a number of EEG-based interaction tasks, including alpha waves, steady-state visual evoked potential analysis, and motor movement classification. Furthermore, we demonstrate an EEG-based biometric subject recognition task, where we reach a sensitivity and specificity of 98.87% and 99.86% respectively, with only 8 EEG channels and an energy consumption per inference on the edge as low as 121 μJ. Moreover, in an EOG-based eye movement classification task, we reach an accuracy of 96.68% on 11 classes, resulting in an information transfer rate of 94.78 bit/min, which can be further increased to 161.43 bit/min by reducing the accuracy to 81.43%. The deployed implementation has an energy consumption of 40 μJ per inference and a total system power of only 12.4 mW, of which only 1.61% is used for classification, allowing for continuous operation of more than 22 h with a small 75 mAh battery.

Cognitive navigation, a high-level and crucial function for organisms' survival in nature, enables autonomous exploration and navigation within the environment. However, most existing works for bio-inspired navigation are implemented with non-neuromorphic computing. This work proposes a bio-inspired memristive spiking neural network (SNN) circuit for goal-oriented navigation, capable of online decision-making through reward-based learning. The circuit comprises three primary modules. The place cell module encodes the agent's spatial position in real-time through Poisson spiking; the action cell module determines the direction of subsequent movement; and the reward-based learning module provides a bio-inspired learning method adaptive to delayed and sparse rewards. To facilitate practical application, the entire SNN is quantized and deployed on a real memristive hardware platform, achieving about a 21× reduction in energy consumption compared to a typical digital acceleration system in the forward computing phase. This work offers an implementation idea of neuromorphic solution for robotic navigation application in low-power scenarios.

Personalized brain implants have the potential to revolutionize the treatment of neurological disorders and augment cognition. Medical implants that deliver therapeutic stimulation in response to detected seizures have already been deployed for the treatment of epilepsy. These devices require low-power integrated circuits for life-long operation. This constraint impedes the integration of machine-learning driven classifiers that could improve treatment outcomes. This paper introduces BrainForest, a neuromorphic multiplier-less bit-serial weight-memory-optimized brain-state classification processor. The architecture achieves state-of-the-art energy efficiency using two layers of neuron models to implement the spectral and temporal functions needed for classification: 1) resonate-and-fire neurons are used to extract physiological signal band energy EEG biomarkers 2) leaky integrator neurons are used to build multi-timescale representations for classification. Sparse neural model firing activity is used to clock-gate device logic, thereby decreasing power consumption by 93%. An energy-optimized 1024-tree boosted decision forest performs the classification used to trigger stimulation in response to detected pathological brain states. The IC is implemented in 65nm CMOS with state-of-the-art power consumption (best case: 9.6μW, typical: 118μW), achieving a seizure sensitivity of 97.5% with a false detection rate of 2.08 per hour.

This article presents a fully integrated CMOS ferrofluidic platform featuring on-chip three-electrode electrochemical cells, temperature regulators, and magnetic sensors. The proposed platform consists of 25 ferrofluidic pixels and 2 magnetic sensors. Each ferrofluidic pixel comprises a spiral inductor, a three-electrode electrochemical cell, a temperature sensor, and a localized Joule heater. Unlike pneumatic-based platforms, this ferrofluidic platform does not require an external pneumatic pump to drive droplets. Instead, the on-chip spiral inductors generate magnetic fields to manipulate the ferrofluidic droplets. Additionally, these inductors are repurposed as heat radiators. The CMOS ferrofluidic platform is implemented using a 45-nm CMOS SOI process. Theoretical analyses of ferrofluidic control and magnetic sensing are conducted to understand the relationship between ferrofluidic movement conditions and the integrated magnetic sensor. The on-chip electrochemical potentiostat is characterized using various concentrations of methylene blue solution, and the variation in the electrochemical sensor is measured. As proof of concept, biological measurements with on-chip real-time recombinase polymerase amplification (RT-RPA) are demonstrated. The proposed platform offers a fully integrated solution for ferrofluidic manipulation, sensing, and temperature regulation without the need for external bulky equipment, thereby supporting advanced biomolecular processing. While RT-RPA is used here solely for demonstration purposes, our ferrofluidic multi-functional CMOS array platform is also capable of processing a wide range of other molecular analytes. This versatility underscores the platform's potential for broad applications in molecular diagnostics and bioanalytical research.

This paper presents a 9-mW ultrasonic through-transmission transceiver (TRX) for portable, non-invasive intracranial pressure (ICP) sensing. It employs two ultrasound transducers placed at the temporal bone windows to measure changes in the ultrasonic time-of-flight (ToF), based on which the skull expansion and the corresponding ICP waveform are derived. Key components include a high-efficiency Class-DE power amplifier (PA) with 95% efficiency and an output swing of 15.8 VPP, along with a successive approximation register (SAR) delay-locked loop (DLL)-based time-to-digital converter (TDC) with 29.8 ps resolution and 122 ns range. Other than electrical characterization, the sensor is validated through two demonstrations using a water tank setup and a human head phantom setup, respectively. It demonstrates a high correlation of R = 0.93 with a medical-grade invasive ICP sensor. The proposed system offers high accuracy, low power consumption, and reliable performance, making it a promising solution for real-time, portable, non-invasive ICP monitoring in various clinical settings.

This paper presents a reconfigurable bidirectional wireless power and data transceiver (RB-WPDT) integrated circuit (IC) for wearable biomedical applications. The proposed transceiver can be reconfigured as a differential class-D power amplifier or a full-wave rectifier depending on the mode signal to facilitate power transfer between devices. Additionally, the RBWPDT system supports full-duplex (FD) data transmission via a single inductive link, enabling real-time control and monitoring between devices. The proposed FD method utilizes frequency shift-keying pulse-width modulation (FSK-PWM) for downlink and load shift-keying (LSK) for uplink, achieving simultaneous bidirectional data transmission by ensuring that the FSK-PWM downlink and LSK uplink data channels operate independently with minimal interference. The measured downlink and uplink data rates are 250 kb/s and 67 kb/s, respectively. The measured overall DC-to-DC efficiency is 49%, while the power delivered to the load (PDL) is 120 mW at a 5 mm distance. The proposed chip is fabricated using a 180-nm BCD CMOS process.

In this article, we present a novel approach for designing a low-power, low-area impulse radio ultra-wideband (IR-UWB) noncoherent receiver capable of achieving a data rate of 100 Mbps. Our proposed receiver demonstrates the ability to demodulate ON-OFF keying pulse streams across the entire lower frequency band defined by the Federal Communication Commission for UWB applications. The key components of the proposed receiver include a reconfigurable differential two-stage low-noise amplifier, a fully differential squarer, narrow-band interface rejection filters, and variable gain baseband amplifiers. These circuits work cohesively to ensure efficient signal reception and processing. To validate the performance of the proposed receiver, we implemented the design using TSMC 40-nm CMOS process technology. A short-range communication including a 1.5 cm tissue layer is tested utilizing a typical upconversion UWB transmitter fabricated in the same technology. Remarkably, the proposed receiver achieves a data rate of 100 Mbps with an impressively low energy efficiency of 78.8 pJ/b and occupies an area of 0.705 mm. The compact size, remarkable energy efficiency, and high data rate capabilities of the proposed receiver meet the stringent requirements of neural recording implants.

This paper presents an adaptive active rectifier with digital feedback delay controllers (DFDC) which quickly tracks optimal on/off timing against input voltage and load variations. To efficiently generate the on/off transition, the proposed active rectifier adopts dynamically controlled coarse/fine delay lines rather than using conventional power-hungry static comparators, while removing the risk of unwanted multiple driving pulses to pass transistors. DFDC conducts the dual-loop digital feedback to independently adjust on/off timing with high-speed 13.56-MHz loop bandwidth, improving the voltage conversion ratio (VCR) and power conversion efficiency (PCE). DFDC can enable real-time power-saving mode control that automatically masks clock-toggling to non-essential blocks to minimize dynamic power loss while driving power transistors. To validate the efficacy of the proposed adaptive rectifier during digital feedback and settling procedures, experiments were carried out with 0.25 μm CMOS prototype at the carrier frequency of 13.56-MHz, input voltages between 1.7 and 2.6 V, and load ranges from 0.33 to 2.2 kΩ. The proposed active rectifier employing DFDC achieves a peak PCE of 93.5% and the peak VCR of 96.3% at the output power of 12.52 mW and 2.02 mW, respectively.

Driven by the progress in efficient embedded processing, there is an accelerating trend toward running machine learning models directly on wearable Brain-Machine Interfaces (BMIs) to improve portability and privacy and maximize battery life. However, achieving low latency and high classification performance remains challenging due to the inherent variability of electroencephalographic (EEG) signals across sessions and the limited onboard resources. This work proposes a comprehensive BMI workflow based on a CNN-based Continual Learning (CL) framework, allowing the system to adapt to inter-session changes. The workflow is deployed on a wearable, parallel ultra-low power BMI platform (BioGAP). Our results based on two in-house datasets, Dataset A and Dataset B, show that the CL workflow improves average accuracy by up to 30.36% and 10.17%, respectively. Furthermore, when implementing the continual learning on a Parallel Ultra-Low Power (PULP) microcontroller (GAP9), it achieves an energy consumption as low as 0.45mJ per inference and an adaptation time of only 21.5 ms, yielding around 25 h of battery life with a small 100 mAh, 3.7 V battery on BioGAP. Our setup, coupled with the compact CNN model and on-device CL capabilities, meets users' needs for improved privacy, reduced latency, and enhanced inter-session performance, offering good promise for smart embedded real-world BMIs.

Electron paramagnetic resonance (EPR) is a powerful spectroscopic technique that allows direct detection and characterization of radicals containing unpaired electron(s). The development of portable, low-power EPR sensing modalities has the potential to significantly expand the utility of EPR in a broad range of fields, ranging from basic science to practical applications such as point-of-care diagnostics. The two major methodologies of EPR are continuous-wave (CW) EPR, where the frequency or field is swept with a constant excitation, and pulse EPR, where short pulses induce a transient signal. In this work, we present the first realization of a fully integrated pulse EPR spectrometer on-chip. The spectrometer utilizes a subharmonic direct-conversion architecture that enables an on-chip oscillator to be used as a dual-mode EPR sensing cell, capable of both CW and pulse-mode operation. An on-chip reference oscillator is used to injection-lock the sensor to form pulses and also to downconvert the pulse EPR signal. A proof-of-concept spectrometer IC with two independent sensing cells is presented, which achieves a pulse sensitivity of 4.6 x 10 spins (1000 averages) and a CW sensitivity of 2.9 x 10 spins/ √{Hz} and can be powered and controlled via a computer USB interface. The sensing cells consume as little as 2.1mW (CW mode), and the system is tunable over a wide frequency range of 12.8-14.9GHz (CW/pulse). Single-pulse free induction decay (FID), two-pulse inversion recovery, two-pulse Hahn echo, three-pulse stimulated echo, and CW experiments demonstrate the viability of the spectrometer for use in portable EPR sensing.

Simultaneous electrophysiological and chemical recording allows for multi-modal neural instrumentation and provides insights into chemical synapses and ion channels across the cell membrane. However, intermodal interference can hinder highly synchronized recording in large-scale systems with high temporal and spatial resolution. In this work, we propose a 1024-channel lab-on-CMOS system for dual-modal neural recording with in-pixel digitization and interference suppression. A foreground calibration scheme with tunable capacitance is implemented in-pixel to compensate for the crosstalk between electrical and chemical recording. Active pixels for both electrical and chemical modalities are designed based on a pulse width modulation (PWM) analog-to-digital conversion scheme. CMOS-compatible post-processing is implemented to realize in-pixel electrodes and chemical sensing membranes. The prototype, implemented in a 180nm CMOS technology, occupies a total area of 33mm with 1024 pixels, and each unit pixel includes one electrical recording site and two chemical recording sites, with dimensions of 150μm×130 μm. The total system power consumption is 19.68mW at a frame rate of 9k and 3k for electrical and chemical imaging respectively. The in-vitro experiment demonstrated the concurrent high density electrophysilogical and electrochemical recording with sub millisecond temporal resolution.

Ultrasound-based Hand Gesture Recognition has gained significant attention in recent years. While static gesture recognition has been extensively explored, only a few works have tackled the task of movement regression for real-time tracking, despite its importance for the development of natural and smooth interaction strategies. In this paper, we demonstrate the regression of 3 hand-wrist Degrees of Freedom (DoFs) using a lightweight, A-mode-based, truly wearable US armband featuring four transducers and WULPUS, an ultra-low-power acquisition device. We collect US data, synchronized with an optical motion capture system to establish a ground truth, from 5 subjects. We achieve state-of-the-art performance with an average root-mean-squared-error (RMSE) of 7.32◦ ± 1.97◦ and mean-absolute-error (MAE) of 5.31◦ ± 1.42◦. Additionally, we demonstrate, for the first time, robustness with respect to transducer repositioning between acquisition sessions, achieving an average RMSE value of 11.11◦ ± 4.14◦ and a MAE of 8.46◦ ± 3.58◦. Finally, we deploy our pipeline on a real-time low-power microcontroller, showcasing the first instance of multi-DoF regression based on A-mode US data on an embedded device, with a power consumption lower than 30mW and end-to-end latency of ≈ 80 ms.

This paper proposes a low-power, high-speed impulse radio-ultra-wideband (IR-UWB) transceiver for brain computer interfaces (BCIs) using amplitude and synchronized time shift keying technique (ASTSK). The proposed IR-UWB transmitter (Tx) generates two pulses (sync pulse and data pulse) per symbol rate. The time difference between two pulses is used for synchronized time shift keying and the amplitude of the two pulses is used for amplitude shift keying. The receiver (Rx) demodulates the time difference with a low power time-to-digital converter (TDC) and peak detector (PD) based amplitude demodulation is suggested to relax analog-to-digital converter (ADC) burden for low power receiver. Especially the Tx-based synchronized operation eliminates the need for complex clock circuitry such as phase-lock loop (PLL) and reference crystal oscillator. Therefore, it can achieve low power and high-speed operation. The prototype, fabricated in 65 nm CMOS, has a frequency range of 6-9 GHz, communication speed of 1.28 Gbps, and power consumption of 18 mW (Tx) and 58 mW (Rx). This work is a fully integrated RF transceiver adapted for high-order modulation and designed to include the receiver.

This article proposes an analog neuromorphic system that enhances symmetry, linearity, and endurance by using a high-precision current readout circuit for multi-bit nonvolatile electro-chemical random-access memory (ECRAM). For on-chip training and inference, the system uses activation modules and matrix processing units to manage analog update/read paths and perform precise output sensing with feedback-based current scaling on the ECRAM array. The 250nm CMOS neuromorphic chip was tested with a 32 x 32 ECRAM synaptic array, achieving linear and symmetric updates and accurate read operations. The proposed circuit system updates the 32 x 32 ECRAM across 100 levels, maintaining consistent synaptic weights, and operates with an output error rate of up to 2.59% per column. It consumes 5.9 mW of power excluding the ECRAM array and achieves 97.3% inference accuracy on the MNIST dataset, close to the software-confirmed 97.78%, with only the final layer (64 x 10) mapped to the ECRAM.

We introduce a bioelectronic interface between biological electrogenic cells and a mixed-signal CMOS integrated circuit with an array of surface electrodes, where not only is the CMOS electrode array capable of electrophysiological recording and stimulation of the cells with 1,024 recording and stimulation channels, but it can also provide low-latency artificial signal pathways from cells it records to cells it stimulates. This on-chip closed-loop modulation has an intrinsic latency less than 5 μs. To demonstrate the utility of the on-chip closed loop modulation as an artificial feedback pathway between biological cells, we develop a silicon-cardiomyocyte self-sustained oscillator with a tunable frequency to which both the relevant part of the CMOS chip and cells are locked, and also a silicon-neuron interface with a silicon inhibitory connection between neuronal cells. This line of cyto-silicon hybrid system, where the boundary between biological and semiconductor systems is blurred, may find applications in prosthesis, brain-machine interface, and fundamental biology research.

Wireless minimally invasive bioelectronic implants enable a wide range of applications in healthcare, medicine, and scientific research. Magnetoelectric (ME) wireless power transfer (WPT) has emerged as a promising approach for powering miniature bio-implants because of its remarkable efficiency, safety limit, and misalignment tolerance. However, achieving low-power and high-quality uplink communication using ME remains a challenge. This paper presents a pulse-width modulated (PWM) ME backscatter uplink communication enabled by a switched-capacitor energy extraction (SCEE) technique. The SCEE rapidly extracts and dissipates the kinetic energy within the ME transducer during its ringdown period, enabling time-domain PWM in ME backscatter. Various circuit techniques are presented to realize SCEE with low power consumption. This paper also describes the high-order modeling of ME transducers to facilitate the design and analysis, which shows good matching with measurement. Our prototyping system includes a millimeter-scale ME implant with a fully integrated system-on-chip (SoC) and a portable transceiver for power transfer and bidirectional communication. SCEE is proven to induce >50% amplitude reduction within 2 ME cycles, leading to a PWM ME backscatter uplink with 17.73 kbps data rate and 0.9 pJ/bit efficiency. It also achieves 8.5 × 10 bit-error-rate (BER) at a 5 cm distance, using a lightweight multi-layer-perception (MLP) decoding algorithm. Finally, the system demonstrates continuous wireless neural local-field potential (LFP) recording in an in vitro setup.

The realization of brain-scale spiking neural networks (SNNs) is impeded by power constraints and low integration density. To address these challenges, multi-core SNNs are utilized to emulate numerous neurons with high energy efficiency, where spike packets are routed through a network-on-chip (NoC). However, the information can be lost in the NoC under high spike traffic conditions, leading to performance degradation. This work presents NEXUS, a 16-core SNN with a diamond-shaped NoC topology fabricated in 28-nm CMOS technology. It integrates 4096 leaky integrate-and-fire (LIF) neurons with 1M 4-bit synaptic weights, occupying an area of 2.16 mm2. The proposed NoC architecture is scalable to any network size, ensuring no data loss due to contending packets with a maximum routing latency of 5.1μs for 16 cores. The proposed congestion management method eliminates the need for FIFO in routers, resulting in a compact router footprint of 0.001 mm. The proposed neurosynaptic core allows for increasing the processing speed by up to 8.5× depending on input sparsity. The SNN achieves a peak throughput of 4.7 GSOP/s at 0.9 V, consuming a minimum energy per synaptic operation (SOP) of 3.3 pJ at 0.55 V. A 4-layer feed-forward network is mapped onto the chip, classifying MNIST digits with 92.3% accuracy at 8.4Kclassification/ s and consuming 2.7-μJ/classification. Additionally, an audio recognition task mapped onto the chip achieves 87.4% accuracy at 215-μJ/classification.