This paper presents a temperature compensated RC oscillator (TC-RCO) designed in 130 nm CMOS technology using regular transistors. The TC-RCO uses constant transconductance biasing for first order temperature compensation. Device mismatch based offset correction and delay compensation techniques in the comparator are used to improve temperature instability by cancelling out second order effects. The oscillator achieves a minimum temperature stability down to 21 ppm/°C for a temperature range of -20 to 100 °C. In the lowest power mode, the oscillator consumes 254 nW power with a 1 V supply. The TC-RCO is operated in two modes, a low power mode that consumes an average of 254 nW and a high stability mode that consumes an average of 345 nW. A duty-cycling technique is used to correct offset after four cycles of oscillation. The oscillator exhibits long term stability of 10 ppm after 1 s integration time.

This paper describes an adaptive noise generator circuit suitable for on-chip simulations of stochastic chemical kinetics. The circuit uses amplified BJT white noise and adaptive low-pass filtering to emulate the power spectrum and autocorrelation of random telegraph signals (RTS) with Poisson-distributed level transitions. A current-mode implementation in the AMS 0.35 m BiCMOS process shows excellent agreement with theoretical results from the Gillespie stochastic simulation algorithm over a 60 dB range in mean current levels (modeling molecule count numbers). The circuit has an estimated layout area of 0.032 mm and typically consumes 400 A, which are 73% and 50% less, respectively, than prior implementations. Moreover, it does not require any off-chip capacitors. Experimental results from a discrete board-level implementation of the circuit are in good agreement with theoretical predictions.

This paper presents a new technique of radio frequency (RF) signal strength detection with a received signal strength indicator (RSSI) circuit which can be deployed in an internet-of-things (IoT) network. The proposed RSSI circuit is based on a direct conversion of RF to digital code indicating the signal strength. The direct conversion is achieved by the repeated switching of a rectifier's output voltage using an ultra-low power comparator. A 5-bit programmable feedback circuit is used to correct detection inaccuracies. The RSSI circuit is implemented in a 65-nm CMOS process and consumes 6nW power. It has a linear dynamic range of 26dB and exhibits an error of ±0.5dB with a wide bandwidth of 750MHz. A detailed analysis of the RSSI circuit is presented and verified with simulation and measurement results. The high detection accuracy with ultra-low power consumption of our RSSI circuit is favourable for IoT applications including localization, beamforming, hardware security and other low-power applications.

Digital cameras expose and readout all pixels in accordance with a global sample clock. This rigid global control of exposure and sampling is problematic for capturing scenes with large variance in brightness and motion, and may cause regions of motion blur, under- and overexposure. To address these issues, we developed a CMOS imaging system that automatically adjusts each pixel's exposure and sampling rate to fit local motion and brightness. This system consists of an image sensor with pixel-addressable exposure configurability in combination with a real-time, per-pixel exposure controller. It operates in a closed-loop to sample, detect and optimize each pixel's exposure and sampling rate for optimal acquisition. Per-pixel exposure control is implemented using all-integrated electronics without external optical modulation. This reduces system complexity and power consumption compared to existing solutions. Implemented using standard 130nm CMOS process, the chip has 256 × 256 pixels and consumes 7.31mW. To evaluate performance, we used this system to capture scenes with complex lighting and motion conditions that would lead to loss of information for globally-exposed cameras. These results demonstrate the advantage of pixel-wise adaptive imaging for a range of computer vision tasks such as segmentation, motion estimation and object recognition.

There is a growing demand for the development of new types of implantable optoelectronics to support both basic neuroscience and optogenetic treatments for neurological disorders. Target specification requirements include multi-site optical stimulation, programmable radiance profile, safe operation, and miniaturization. It is also preferable to have a simple serial interface rather than large numbers of control lines. This paper demonstrates an optrode structure comprising of a standard complementary metal-oxide-semiconductor process with 18 optical stimulation drivers. Furthermore, diagnostic sensing circuitry is incorporated to determine the long-term functionality of the photonic elements. A digital control system is incorporated to allow independent multisite control and serial communication with external control units.

This paper describes an on-chip interface for recovering power and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. The target application requires two modules to be implanted in the brain (cortex) and upper chest; connected via a subcutaneous lead. The brain implant consists of multiple identical "optrodes" that facilitate a bidirectional neural interface (electrical recording and optical stimulation), and the chest implant contains the power source (battery) and processor module. The proposed interface is integrated within each optrode ASIC allowing full-duplex and fully-differential communication based on Manchester encoding. The system features a head-to-chest uplink data rate (up to 1.6 Mbps) that is higher than that of the chest-to-head downlink (100 kbps), which is superimposed on a power carrier. On-chip power management provides an unregulated 5-V dc supply with up to 2.5-mA output current for stimulation, and two regulated voltages (3.3 and 3 V) with 60-dB power supply rejection ratio for recording and logic circuits. The 4-wire ASIC has been implemented in a 0.35-[Formula: see text] CMOS technology, occup-ying a 1.5-mm silicon area, and consumes a quiescent current of [Formula: see text]. The system allows power transmission with measured efficiency of up to 66% from the chest to the brain implant. The downlink and uplink communication are successfully tested in a system with two optrodes and through a 4-wire implantable lead.

A parallel micro-power mixed-signal VLSI implementation of independent component analysis (ICA) with reconfigurable outer-product learning rules is presented. With the gradient sensing of the acoustic field over a miniature microphone array as a pre-processing method, the proposed ICA implementation can separate and localize up to 3 sources in mild reverberant environment. The ICA processor is implemented in 0.5 µm CMOS technology and occupies 3 mm × 3 mm area. At 16 kHz sampling rate, ASIC consumes 195 µW power from a 3 V supply. The outer-product implementation of natural gradient and Herault-Jutten ICA update rules demonstrates comparable performance to benchmark FastICA algorithm in ideal conditions and more robust performance in noisy and reverberant environment. Experiments demonstrate perceptually clear separation and precise localization over wide range of separation angles of two speech sources presented through speakers positioned at 1.5 m from the array on a conference room table. The presented ASIC leads to a extreme small form factor and low power consumption microsystem for source separation and localization required in applications like intelligent hearing aids and wireless distributed acoustic sensor arrays.

In this paper we present a fixed window level crossing sampling analog to digital convertor for bio-potential recording sensors. This is the first proposed and fully implemented fixed window level crossing ADC without local DACs and clocks. The circuit is designed to reduce data size, power, and silicon area in future wireless neurophysiological sensor systems. We built a testing system to measure bio-potential signals and used it to evaluate the performance of the circuit. The bio-potential amplifier offers a gain of 53 dB within a bandwidth of 200 Hz-20 kHz. The input-referred rms noise is 2.8 µV. In the asynchronous level crossing ADC, the minimum delta resolution is 4 mV. The input signal frequency of the ADC is up to 5 kHz. The system was fabricated using the AMI 0.5 µm CMOS process. The chip size is 1.5 mm by 1.5 mm. The power consumption of the 4-channel system from a 3.3 V supply is 118.8 µW in the static state and 501.6 µW with a 240 kS/s sampling rate. The conversion efficiency is 1.6 nJ/conversion.

Inductive coupling is a viable scheme to wirelessly energize devices with a wide range of power requirements from nanowatts in radio frequency identification tags to milliwatts in implantable microelectronic devices, watts in mobile electronics, and kilowatts in electric cars. Several analytical methods for estimating the power transfer efficiency (PTE) across inductive power transmission links have been devised based on circuit and electromagnetic theories by electrical engineers and physicists, respectively. However, a direct side-by-side comparison between these two approaches is lacking. Here, we have analyzed the PTE of a pair of capacitively loaded inductors via reflected load theory (RLT) and compared it with a method known as coupled-mode theory (CMT). We have also derived PTE equations for multiple capacitively loaded inductors based on both RLT and CMT. We have proven that both methods basically result in the same set of equations in steady state and either method can be applied for short- or midrange coupling conditions. We have verified the accuracy of both methods through measurements, and also analyzed the transient response of a pair of capacitively loaded inductors. Our analysis shows that the CMT is only applicable to coils with high quality factor () and large coupling distance. It simplifies the analysis by reducing the order of the differential equations by half compared to the circuit theory.

The modified discrete cosine transform (MDCT) and inverse MDCT (IMDCT) are two of the most computational intensive operations in MPEG audio coding standards. A new mixed-radix algorithm for efficient computing the MDCT/IMDCT is presented. The proposed mixed-radix MDCT algorithm is composed of two recursive algorithms. The first algorithm, called the radix-2 decimation in frequency (DIF) algorithm, is obtained by decomposing an N-point MDCT into two MDCTs with the length N/2. The second algorithm, called the radix-3 decimation in time (DIT) algorithm, is obtained by decomposing an N-point MDCT into three MDCTs with the length N/3. Since the proposed MDCT algorithm is also expressed in the form of a simple sparse matrix factorization, the corresponding IMDCT algorithm can be easily derived by simply transposing the matrix factorization. Comparison of the proposed algorithm with some existing ones shows that our proposed algorithm is more suitable for parallel implementation and especially suitable for the layer III of MPEG-1 and MPEG-2 audio encoding and decoding. Moreover, the proposed algorithm can be easily extended to the multidimensional case by using the vector-radix method.

High-throughput electrode arrays are required for advancing devices for testing the effect of drugs on cellular function. In this paper, we present design criteria for a potentiostat circuit that is capable of measuring transient amperometric oxidation currents at the surface of an electrode with submillisecond time resolution and picoampere current resolution. The potentiostat is a regulated cascode stage in which a high-gain amplifier maintains the electrode voltage through a negative feedback loop. The potentiostat uses a new shared amplifier structure in which all of the amplifiers in a given row of detectors share a common half circuit permitting us to use fewer transistors per detector. We also present measurements from a test chip that was fabricated in a 0.5-μm, 5-V CMOS process through MOSIS. Each detector occupied a layout area of 35μm × 15μm and contained eight transistors and a 50-fF integrating capacitor. The rms current noise at 2kHz bandwidth is ≈ 110fA. The maximum charge storage capacity at 2kHz is 1.26 × 10(6) electrons.

Temperature detection using microwave radiometry has proven value for noninvasively measuring the absolute temperature of tissues inside the body. However, current clinical radiometers operate in the gigahertz range, which limits their depth of penetration. We have designed and built a noninvasive radiometer which operates at radio frequencies (64 MHz) with ∼100-kHz bandwidth, using an external RF loop coil as a thermal detector. The core of the radiometer is an accurate impedance measurement and automatic matching circuit of 0.05 Ω accuracy to compensate for any load variations. The radiometer permits temperature measurements with accuracy of ±0.1°K, over a tested physiological range of 28° C-40° C in saline phantoms whose electric properties match those of tissue. Because 1.5 T magnetic resonance imaging (MRI) scanners also operate at 64 MHz, we demonstrate the feasibility of integrating our radiometer with an MRI scanner to monitor RF power deposition and temperature dosimetry, obtaining coarse, spatially resolved, absolute thermal maps in the physiological range. We conclude that RF radiometry offers promise as a direct, noninvasive method of monitoring tissue heating during MRI studies and thereby providing an independent means of verifying patient-safe operation. Other potential applications include titration of hyper- and hypo-therapies.

This paper describes a low-power approach to capacitive sensing that achieves a high signal-to-noise ratio. The circuit is composed of a capacitive feedback charge amplifier and a charge adaptation circuit. Without the adaptation circuit, the charge amplifier only consumes 1 μW to achieve the audio band SNR of 69.34dB. An adaptation scheme using Fowler-Nordheim tunneling and channel hot electron injection mechanisms to stabilize the DC output voltage is demonstrated. This scheme provides a very low frequency pole at 0.2Hz. The measured noise spectrums show that this slow-time scale adaptation does not degrade the circuit performance. The DC path can also be provided by a large feedback resistance without causing extra power consumption. A charge amplifier with a MOS-bipolar pseudo-resistor feedback scheme is interfaced with a capacitive micromachined ultrasonic transducer to demonstrate the feasibility of this approach for ultrasound applications.

We present an approach to design spiking silicon neurons based on dynamical systems theory. Dynamical systems theory aids in choosing the appropriate level of abstraction, prescribing a neuron model with the desired dynamics while maintaining simplicity. Further, we provide a procedure to transform the prescribed equations into subthreshold current-mode circuits. We present a circuit design example, a positive-feedback integrate-and-fire neuron, fabricated in 0.25 μm CMOS. We analyze and characterize the circuit, and demonstrate that it can be configured to exhibit desired behaviors, including spike-frequency adaptation and two forms of bursting.

We present an active full-wave rectifier with offset-controlled high speed comparators in standard CMOS that provides high power conversion efficiency (PCE) in high frequency (HF) range for inductively powered devices. This rectifier provides much lower dropout voltage and far better PCE compared to the passive on-chip or off-chip rectifiers. The built-in offset-control functions in the comparators compensate for both turn-on and turn-off delays in the main rectifying switches, thus maximizing the forward current delivered to the load and minimizing the back current to improve the PCE. We have fabricated this active rectifier in a 0.5-μm 3M2P standard CMOS process, occupying 0.18 mm(2) of chip area. With 3.8 V peak ac input at 13.56 MHz, the rectifier provides 3.12 V dc output to a 500 Ω load, resulting in the PCE of 80.2%, which is the highest measured at this frequency. In addition, overvoltage protection (OVP) as safety measure and built-in back telemetry capabilities have been incorporated in our design using detuning and load shift keying (LSK) techniques, respectively, and tested.