Accelerated testing must address the failure mechanisms active within the devices undergoing tests in order to assess lifetimes in a meaningful way. The assumption of constant temperature, thermally activated lifetime, based upon the Arrhenius assumptions, does not always provide the necessary understanding to interpret accelerated tests in microelectronics. Plastic encapsulants, dielectric polymers, and underfill materials are subject to delamination and cracking with thermal cycling. Crack propagation during use environment exposure, drives the potential for failure of microelectronic devices and is therefore a necessary focal point in qualification and life testing. This paper reviews the available research in the application of fracture mechanics to this class of problems in microelectronics including relevant test data. In addition, useful acceleration factor models are derived for polymer crack propagation based on principles of linear elastic fracture mechanics. Further, a simple approach to estimating the minimum temperature cycling ranges, necessary to propagate a crack, is also presented. Finally, a methodology of applying acceleration factors to develop testing plans is shown, with an example in spaceflight for a cubesat in low Earth orbit. Overall, this is a paper that shows a useful and appropriate process for creating physics of failure based life testing for delamination and cracking failures in microelectronic polymers in a temperature cycling environment.

Electromigration induced failure development in a copper dual-damascene structure with a through silicon via (TSV) located at the cathode end of the line is studied. The resistance change caused by void growth under the TSV and the interconnect lifetime estimation are modeled based on analytical expressions and also investigated with the help of numerical simulations of fully three-dimensional structures. It is shown that, in addition to the high resistance increase caused by a large void, a small void under the TSV can also lead to a significant resistance increase, particularly in the presence of imperfections at the TSV bottom introduced during the fabrication process. As a consequence, electromigration failure in such structures is likely to have bimodal characteristics. The simulation results have indicated that both modes are important to be considered in order to obtain a more precise description of the interconnect lifetime distribution.

A compact model for early electromigration failures in copper dual-damascene interconnects is proposed. The model is based on the combination of a complete void nucleation model together with a simple mechanism of slit void growth under the via. It is demonstrated that the early electromigration lifetime is well described by a simple analytical expression, from where a statistical distribution can be conveniently obtained. Furthermore, it is shown that the simulation results provide a reasonable estimation for the lifetimes.

Degradation of CMOS NAND logic circuits resulting from dielectric degradation of a single pMOSFET using constant voltage stress has been examined by means of a switch matrix technique. As a result, the NAND gate rise time increases by greater than 65%, which may lead to timing errors in high frequency digital circuits. In addition, the NAND gate DC switching point voltage shifts by nearly 11% which may be of consequence for analog or mixed signal applications. Experimental results for the degraded pMOSFET reveal a decrease in drive current by approximately 43%. There is also an increase in threshold voltage by 23%, a decrease in source to drain conductance of 30%, and an increase in channel resistance of about 44%. A linear relationship between the degradation of the pMOSFET channel resistance and the increase in NAND gate rise time is demonstrated, thereby providing experimental evidence of the impact of a single degraded pMOSFET on NAND circuit performance.