This work reports on three speed optimized pnp bipolar phototransistors build in a standard 180 nm CMOS process using a special starting wafer. The starting wafer consists of a low doped p epitaxial layer on top of the p substrate. This low doped p epitaxial layer leads to a thick space-charge region between base and collector and thus to a high -3 dB bandwidth at low collector-emitter voltages. For a further increase of the bandwidth the presented phototransistors were designed with small emitter areas resulting in a small base-emitter capacitance. The three presented phototransistors were implemented in sizes of 40 × 40 μm and 100 × 100 μm. Optical DC and AC measurements at 410 nm, 675 nm and 850 nm were done for phototransistor characterization. Due to the speed optimized design and the layer structure of the phototransistors, bandwidths up to 76.9 MHz and dynamic responsivities up to 2.89 A/W were achieved. Furthermore simulations of the electric field strength and space-charge regions were done.

The paper addresses the passivation of Germanium surfaces by using layered LaO/ZrO high- dielectrics deposited by Atomic Layer Deposition to be applied in Ge-based MOSFET devices. Improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing ambient during thermal post treatment in presence of thin Pt cap layers are demonstrated. The results suggest the formation of thin intermixed La Ge O interfacial layers with thicknesses controllable by oxidation time. This formation is further investigated by XPS, EDX/EELS and TEM analysis. An additional reduction annealing treatment further improves the electrical properties of the gate dielectrics in contact with the Ge substrate. As a result low interface trap densities on (1 0 0) Ge down to 3 × 10 eV cm are demonstrated. The formation of the high- La Ge O layer is in agreement with the oxide densification theory and may explain the improved interface trap densities. The scaling potential of the respective layered gate dielectrics used in Ge-based MOS-based device structures to EOT of 1.2 nm or below is discussed. A trade-off between improved interface trap density and a lowered equivalent oxide thickness is found.

We present a model based on  ·  theory which is able to capture the subband structure effects present in ultra-thin strained silicon nanowires. For electrons, the effective mass and valley minima are calculated for different crystal orientations, thicknesses, and strains. The actual enhancement of the transport properties depends highly on the crystal orientation of the nanowire axis; for certain orientations strain and confinement can play together to give a significant increase of the electron mobility. We also show that the effects of both strain and confinement on mobility are generally more pronounced in nanowires than in thin films. We show that optimal transport properties can be expected to be achieved through a mix of confinement and strain. Our results are in good agreement with recent experimental findings.

The potential of strained DOTFET technology is demonstrated. This technology uses a SiGe island as a stressor for a Si capping layer, into which the transistor channel is integrated. The structure information of fabricated samples is extracted from atomic force microscopy (AFM) measurements. Strain on the upper surface of a 30 nm thick Si layer is in the range of 0.7%, as supported by finite element calculations. The Ge content in the SiGe island is 30% on average, showing an increase towards the top of the island. Based on the extracted structure information, three-dimensional strain profiles are calculated and device simulations are performed. Up to 15% enhancement of the NMOS saturation current is predicted.

One-dimensional nanostructures such as silicon nanowires (SiNW) are attractive candidates for low power density electronic and optoelectronic devices including sensors. A new simple method for SiNW bulk synthesis[1, 2] is demonstrated in this work, which is inexpensive and uses low toxicity materials, thereby offering a safe, energy efficient and green approach. The method uses low flammability liquid phenylsilanes, offering a safer avenue for SiNW growth compared with using silane gas. A novel, duo-chamber glass vessel is used to create a low-pressure environment where SiNWs are grown through vapor-liquid-solid mechanism using gold nanoparticles as a catalyst. The catalyst decomposes silicon precursor vapors of diphenylsilane and triphenylsilane and precipitates single crystal SiNWs, which appear to grow parallel to the substrate surface. This opens up possibilities for synthesizing nano-junctions amongst wires which is important for the grid architecture of nanoelectronics proposed by Likharev[3]. Even bulk synthesis of SiNW is feasible using sacrificial substrates such as CaCO(3) that can be dissolved post-synthesis. Furthermore, by dissolving appropriate dopants in liquid diphenylsilane, a controlled doping of the nanowires is realized without the use of toxic gases and expensive mass flow controllers. Upon boron doping, we observe a characteristic red shift in photoluminescence spectra. In summary, an inexpensive and versatile method for SiNW is presented that makes these exotic materials available to any lab at low cost.

CMOS compatible, high voltage SOI MESFETs have been fabricated using a standard 3.3V CMOS process without any changes to the process flow. A 0.6μm gate length device operates with a cut-off frequency of 7.3GHz and a maximum oscillation frequency of 21GHz. There is no degradation in device performance up to its breakdown voltage, which greatly exceeds that of CMOS devices on the same process. Other figures of merit of relevance to RF front-end design are presented, including the maximum stable gain and noise figure. An accurate representation of the device in SPICE has been developed using the commercially available TOM3 model. Using the SOI MESFET model, a source degenerated low noise RF amplifier targeting operation near 1GHz has been designed. The amplifier was fabricated on a PCB board and operates at 940MHz with a minimum NF of 3.8dB and RF gain of 9.9dB while only consuming 5mW of DC power.

We have fabricated and tested the performance of sub-50nm gate nMOSFETs to assess their suitability for mixed signal applications in the super high frequency (SHF) band, i.e. 3-30GHz. For a 30nm×40 μm×2 device, we found f(T) =465GHz at V(ds)=2V, V(g)=0.67V, which is the highest cut-off frequency reported for a MOSFET produced on bulk silicon substrate so far. However, our measurements of f(max) and noise figure indicate that parasitics impose limitations on SHF operation. We also present a high-frequency ac model appropriate to sub-50nm gate length nanotransistors, which incorporates the effects of the parasitics. The model accurately accounts for measurements of the S and Y parameters in the frequency range from 1 to 50GHz.

The inevitable current overshoot which follows forming in filamentary RRAM devices is often perceived as a source of variability that should be minimized. This sentiment has led to efforts to curtail the overshoot by decreasing the parasitic capacitance using highly integrated 1T-1R or 1R-1R device structures. While this is readily achievable in single device test structures, it poses an intricate design constraint for memory array designs. Several papers (Degraeve et al., 2010, 2014; Fantini et al., 2013; Raghavan et al., 2013; Padovani et al., 2015) suggest that there is insufficient current to form stable filaments for small parasitic capacitances and/or low current compliance levels. Thus, the relationship between minimizing overshoot current and improved filament stability is tenuous. In this study, we utilize the forming energy-based understanding of filamentary forming to reveal that the parasitic capacitance should be optimized, rather than minimized for better filament control.